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data sheet (v3) 2005 oct 03 SDN0080G 80-segment dot-matrix stn lcd driver to improve design and/or performance, avant electronics may make changes to its products. please contac t avant electronics for the latest versions of its products d a t a sh eet
2005 oct 03 2 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 1general 1.1 description the SDN0080G is an 80-segment dot-matrix stn lcd driver. it is to be paired with the sdn8000g 80-common driver. 1.2 features ? ? ? ? ? ? ? ? ? ? ? ? ?
2005 oct 03 3 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 2 functional block diagram and description 2.1 functional block diagram fig.1 functional block diagram v1 v3 v4 v ee dispoff di4 di3 di2 di1 r/l cdi cp load cdo m vss vdd 2nd latch (80 bits) 4bits address decoder address counter chip disable & latch control data bus interface (5 bits) o1 o2 o3 o79 o80 80 4-level lcd driver circuit (80 bits) level shifter (80 bits) 1st latch (80 bits) shift control 80 80 4 20 5 address decoder high voltage area
2005 oct 03 4 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 3 pinning information 3.1 pinning diagram fig.2 pin diagram of qfp100 / lqfp100 package 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 32 33 31 o2 o3 o5 o7 o9 o10 o12 o13 o15 o18 o19 o20 o21 o22 o4 o6 o8 o11 o14 o17 o16 o23 o24 o25 o26 o27 o28 o29 o30 o1 o79 o78 o76 o74 o72 o71 o69 o68 o66 o63 o62 o61 o60 o59 o77 o75 o73 o70 o67 o64 o65 o58 o57 o56 o55 o54 o53 o52 o51 o80 o50 o49 o48 o47 o46 o45 o44 o43 o42 o41 o40 o39 o38 o37 o36 o35 o34 o33 o32 o31 cdi v1 vee v3 dispoff v dd r/l v ss m v4 load nc nc nc di4 di3 di1 cp cdo di2 SDN0080G 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
2005 oct 03 5 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 3.2 signal description table 2 pin signal description. to avoid a latch-up effect at power-on: v ss ?
2005 oct 03 6 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 4 functional description 4.1 segment output drive (o1~o80) the voltage level of the outputs o1~o80 is determined by input data (display data), m (frame signal), and dispoff , as given in the following table. table 3 output voltage level of o1~o80 m data dispoff output l l h v3 l h h v1 h l h v4 h h h v ee x x l v1 in the above table, x= don?t care and must be tied either to h or l. 4.2 display data inputs (di1~di4) the SDN0080G has a 4-bit parallel data bus (di1~di4) to interf ace with a controller. a logi c high of a bit represents an on cell (black pixel on the lcd screen). table 4 data bits display data lcd drive output lcd display h selected level (v1, v ee ) on l unselected level (v3, v4) off 4.3 sequence of data input when r/l=l, the 4-bit data that is firs t latched goes to o77 ~ o80 and the 4-bit data that is last latched goes to o1 ~ o4. when r/l=h, the 4-bit data that is first latched goes to o1 ~ o4 and the 4-bit data that is last latched goes to o77 ~ o80. fig.3 sequence/direction of display data input di1 di2 di3 di4 di1 di2 di3 di4 di1 di2 di3 di4 o1 o2 o3 o4 o5 o6 o7 o8 o77 o78 o79 o80 di1 di2 di3 di4 first latched last latched r/l=l 4 bits di4 di3 di2 di1 di4 di3 di2 di1 di4 di3 di2 di1 o1 o2 o3 o4 o5 o6 o7 o8 o77 o78 o79 o80 di1 di2 di3 di4 last latched first latched r/l=h 4 bits
2005 oct 03 7 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 5 absolute maximum rating table 5 absolute maximum rating v dd = 5 v ? 0 ? >
2005 oct 03 8 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 6 dc characteristics table 6 dc characteristics v dd = 5 v 252 0.0 ? 0.4 ? ? >
2005 oct 03 9 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 7 ac characteristics fig.4 ac characteristics 0.2v dd t setup t hold t d cp 0.8v dd 0.2v dd 0.8v dd 0.2v dd 0.8v dd 0.2v dd 0.8v dd 0.2v dd t d 0.2v dd t cl t lc 0.8v dd 0.2v dd t wc load t r t wl t f 0.2v dd t r t f 0.2v dd cp di1~di4 cdo t wc table 7 ac characteristics v dd = 5 v 25 80 ? < b) t r , t f < 50 ns.
2005 oct 03 10 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 8 output timing diagram fig.5 output timing diagram 1 2 3 19 20 21 ic number 1 data acquisition period ic number 2 data acquisition period ic number 3 data acquisition period ic number n data acquisition period cp di1 di4 load o1~o80 cdo(no.n) cdo(no.3) cdo(no.2) cdo(no.1) one scan line ( n x 80 pixels )
2005 oct 03 11 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 9 timing chart ( 1/240 duty, 1/16 bias) 9.1 1/240 duty timing chart 2 fig.6 1/240 duty timing chart load 01~o80 m load di1~di4 cp d1~d80 m 12 240 1 2 240 1 240 9.2 1/16 bias fig.7 1/16 bias load 240 1 2 240 1 2 240 1 2 latch data m vdd (v1) va vb (v3) l h l l h l l h l o1 ~o80 vc (v4) vd ve (v ee ) va = v dd - (1/16) v lcd vb = v dd - (2/16) v lcd v lcd vc = v dd - (14/16) v lcd vd = v dd - (15/16) v lcd ve = v dd - (16/16) v lcd v lcd vdd v dd v1 v3 v4 vee r r 12r r r va vb vc vd ve vr v ss v ee refer to fig. 8 for enlarged view.
2005 oct 03 12 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 9.3 bias circuit v lcd v dd v dd v1 v3 v4 v ee r r 12r r r va vb vc vd ve vr v ss fig.8 lcd bias voltage v ee SDN0080G va = v dd - (1/16) v lcd vb = v dd - (2/16) v lcd vc = v dd - (14/16) v lcd vd = v dd - (15/16) v lcd ve = v dd - (16/16) v lcd
2005 oct 03 13 of 18 data sheet (v3) 80-segment dot-matrix stn lcd driver SDN0080G avant electronics 10 application circuit (240 x 640 dot) seg338 seg640 seg339 seg1 seg2 seg3 com1 com2 com3 com238 com239 com240 cdo di1~di4 m cp load v1 v3 v4 SDN0080G cdi vdd vss vee dispoff r/l v dd load dc/dc 1/16 bias vref v ee v1 v2 v3 v4 v5 rs/ls dio1 v dd v ss dio80 disp off v1 v5 v2 vee cp m rs/ls dio1 vdd vss dio80 dispoff v1 v5 v2 vee cp m cdo di1~di4 m cp load v1 v3 v4 SDN0080G cdi v dd v ss v ee dispoff r/l v dd cdo di1~di4 cp load v1 v3 v4 SDN0080G cdi v dd v ss v ee dispoff r/l v dd vdd gnd flm dispoff di1~di4 cp m o1~o80 o1~o80 o1~o80 240 x 640 lcd panel (1/240 duty, 1/16 bias) o1~o80 o1~o80 controller sdn8000g sdn8000g in this application, 3 pcs of the sdn8000g and 8 pcs of the SDN0080G are used. m (la5317m) fig.9 typical application circuit
2005 oct 03 14 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 11 pin circuits table 8 mos-level schematics of all input, output, and i/o pins. symbol input/ output circuit notes cdo output vdd vss vss vdd cp, load, di1~di4, r/l, m, cdi, dispoff inputs vss vdd vss vdd o1~o80, v1, v3, v4, v ee driver outputs, high voltage inputs on n= 1 ~ 80 v1 v3 v4 vee vdd en1 en2 en3 vdd vdd vee vee vee vdd v ee en4 vdd vee
2005 oct 03 15 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 12 application notes 1. it is recommended that the following power-up sequence be followed to ensure reliable operation of your display system. as the ics are fabricated in cm os and there is intrinsic latch-up problem associated with any cmos devices, proper power-up sequence can reduce the danger of triggeri ng latch-up. when powering up the system, control logic power must be powered on first. when powering down the system, cont rol logic must be shut off later than or at the same time with the lcd bias (v ee ). vdd signal v ee 5v 0v -30v 0~50 ms 1 second (minimum) 0 second 0 second (minimum) (minimum) 0~50 ms 1 second (minimum) fig.10 recommended power up/down sequence
2005 oct 03 16 of 18 data sheet (v3) 80-segment dot-matrix stn lcd driver SDN0080G avant electronics 13 package information SDN0080G qfp100 package outline drawing
2005 oct 03 17 of 18 data sheet (v3) 80-segment dot-matr ix stn lcd driver SDN0080G avant electronics 14 soldering 14.1 introduction there is no soldering method that is ideal for all ic package s. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circui ts with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. for more in-depth account of soldering ics, please refer to dedicated reference materials. 14.2 reflow soldering reflow soldering techniques ar e suitable for all qfp packages. the choice of heating method may be infl uenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolute ly dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can c ause cracking of the plastic body . for more information, please contact avant for drypack information. reflow soldering requires solder paste (a suspension of fi ne solder particles, flux and bi nding agent) to be applied to the printed-circuit board by screen prin ting, stencilling or pressure-syri nge dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typica l reflow temperatures range from 215 to 250 q c. preheating is necessary to dry the paste and ev aporate the binding agent. preheating duration: 45 minutes at 45 q c. 14.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possib ility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: x a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. x the footprint must be at an angle of 45 q to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 q c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 q c within 6 seconds. typical dwell time is 4 seconds at 250 q c. a mildly-activated flux will elimi nate the need for removal of corrosiv e residues in most applications. 14.4 repairing soldered joints fix the component by first soldering two diagonally- oppos ite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 q c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 q c.
2005 oct 03 18 stn lcd driver data sheet (v3) 80-segment dot-matrix stn lcd driver SDN0080G 15 life support applications these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury . avant customers using or selling these products for use in such applications do so at their ow n risk and agree to fully indemnify avant for any damages resulting from such improper use or sale.

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